Oct 01, 2010 can u help me? I have a problem with digital design as following: 'build a 8 bit up/down counter with I/O: clk, set, reset, data_in, data_out. VHDL program to count upto 10 in 4 bit up counter. That uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL Register Transfer. Up vote 0 down vote.

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity counter is port(CLK, CLR: in std_logic; output: inout std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (CLK, CLR) variable i: integer:=0; begin if (CLR='1') then tmp. Needs to operate off one clock edge Because your counter port has clk in it, we can assume you want the counter to count synchronous to the clock. You're operating off of both clock edges elsif (clk = '1') then should be something like elsif clk'event and clk = '1' then or elsif rising_edge(clk) then These examples use the rising edge of clk. Dubrin Leadership 5th Edition. You can't synthesize something that uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. It's not a recognized clocking method.

Making a modulo 10 counter Under the assumption you want the counter to go from 0 to 9 and rollover this for i in 0 to 6 loop tmp '0'); # equivalent to '0000' else tmp. Download Vt Transaction Plus Keygen Crack.

Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter_VHDL is port( Number: in std_logic_vector(0 to 3); Clock: in std_logic; Load: in std_logic; Reset: in std_logic; Direction: in std_logic; Output: out std_logic_vector(0 to 3) ); end Counter_VHDL; architecture Behavioral of Counter_VHDL is signal temp: std_logic_vector(0 to 3); begin process(Clock,Reset) begin if Reset='1' then temp.